Universal Remote Control R7 - SPECS SHEET Uživatelský manuál Strana 43
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Hodnocené. / 5. Na základě hodnocení zákazníků
Data Sheet ADP5589
Rev. B | Page 43 of 52
CLOCK_DIV_CFG Register 0x43
Table 75. CLOCK_DIV_CFG Bit Descriptions
Bits Name R/W Description
7 Reserved.
6 CLK_INV R/W Inverts the divided down clock signal.
[5: 1] CLK_DIV[4:0] R/W Defines the divide down scale of the externally supplied clock.
00000 = divide by 1 (pass-through).
00001 = divide by 2.
00010 = divide by 3.
00011 = divide by 4.
11111 = divide by 32.
0 CLK_DIV_EN R/W Enables the clock divider circuit to divide down the externally supplied clock signal.
LOGIC_1_CFG Register 0x44
Table 76. LOGIC_1_CFG Bit Descriptions
Bits Name R/W Description
7 Reserved.
6 LY1_INV R/W 0 = LY1 output not inverted before passing into Logic Block 1.
1 = inverts output LY1 from Logic Block 1.
5 LC1_INV R/W 0 = LC1 input not inverted before passing into Logic Block 1.
1 = inverts input LC1 before passing it into Logic Block 1.
4 LB1_INV R/W 0 = LB1 input not inverted before passing into Logic Block 1.
1 = inverts input LB1 before passing it into Logic Block 1.
3 LA1_INV R/W 0 = LA1 input not inverted before passing into Logic Block 1.
1 = inverts input LA1 before passing it into Logic Block 1.
[2: 0] LOGIC1_SEL[2:0] R/W Configures the digital mux for Logic Block 1.
000 = off/disable.
001 = AND1.
010 = OR1.
011 = XOR1.
100 = FF1.
101 = IN_LA1.
110 = IN_LB1.
111 = IN_LC1.
LOGIC_2_CFG Register 0x45
Table 77. LOGIC_2_CFG Bit Descriptions
Bits Name R/W Description
7 LY1_CASCADE R/W 0 = use Input LA2 for Logic Block 2.
1 = use Output LY1 from Logic Block 1 instead of LA2 as the input for Logic Block 2.
The R0 pin can be used as GPIO or key when cascade is in use.
6 LY2_INV R/W 0 = LY2 input not inverted before passing into Logic Block 2.
1 = inverts Output LY2 from Logic Block 2.
5 LC2_INV R/W 0 = LC2 input not inverted before passing into Logic Block 2.
1 = inverts Input LC2 before passing it into Logic Block 2.
4
LB2_INV
R/W
0 = LB2 input not inverted before passing into Logic Block 2.
1 = inverts Input LB2 before passing it into Logic Block 2.
3 LA2_INV R/W 0 = LA2 input not inverted before passing into Logic Block 2.
1 = inverts Input LA2 before passing it into Logic Block 2.
- ADP5589 1
- TABLE OF CONTENTS 2
- SPECIFICATIONS 3
- ABSOLUTE MAXIMUM RATINGS 5
- QUICK DEVICE OVERVIEW 7
- 9714-004 7
- DEVICE ENABLE 8
- DEVICE OVERVIEW 8
- EVENT FIFO 9
- KEY SCAN CONTROL 9
- Rev. B 10
- KEY PRESSED 10
- 09714-009 10
- Data Sheet ADP5589 11
- ADP5589 Data Sheet 12
- Key Pad Extension 12
- Ghosting 12
- FIFO Lock/Unlock 12
- GPI Input 15
- REGISTER INTERFACE 19
- REGISTER MAP 21
- ID Register 0x00 23
- INT_STATUS Register 0x01 23
- Status Register 0x02 23
- FIFO_1 Register 0x03 24
- Rev. B 25
- Rev. B 26
- GPI_INT_STAT_A Register 0x13 27
- GPI_INT_STAT_B Register 0x14 27
- GPI_INT_STAT_C Register 0x15 27
- GPI_STATUS_A Register 0x16 28
- GPI_STATUS_B Register 0x17 28
- GPI_STATUS_C Register 0x18 28
- RPULL_CONFIG_A Register 0x19 29
- RPULL_CONFIG_B Register 0x1A 29
- RPULL_CONFIG_C Register 0x1B 30
- RPULL_CONFIG_D Register 0x1C 30
- RPULL_CONFIG_E Register 0x1D 31
- GPI_EVENT_EN_A Register 0x21 32
- GPI_EVENT_EN_B Register 0x22 33
- GPI_EVENT_EN_C Register 0x23 33
- DEBOUNCE_DIS_A Register 0x27 35
- DEBOUNCE_DIS_B Register 0x28 35
- DEBOUNCE_DIS_C Register 0x29 36
- GPO_DATA_OUT_A Register 0x2A 36
- GPO_DATA_OUT_B Register 0x2B 36
- GPO_DATA_OUT_C Register 0x2C 37
- GPO_OUT_MODE_A Register 0x2D 37
- GPO_OUT_MODE_B Register 0x2E 37
- GPO_OUT_MODE_C Register 0x2F 38
- UNLOCK1 Register 0x33 39
- UNLOCK2 Register 0x34 39
- EXT_LOCK_EVENT Register 0x35 39
- UNLOCK_TIMERS Register 0x36 40
- LOCK_CFG Register 0x37 40
- RESET1_EVENT_A Register 0x38 40
- RESET1_EVENT_B Register 0x39 40
- RESET1_EVENT_C Register 0x3A 41
- RESET2_EVENT_A Register 0x3B 41
- RESET2_EVENT_B Register 0x3C 41
- RESET_CFG Register 0x3D 41
- PWM_OFFT_LOW Register 0x3E 42
- PWM_OFFT_HIGH Register 0x3F 42
- PWM_ONT_LOW Register 0x40 42
- PWM_ONT_HIGH Register 0x41 42
- PWM_CFG Register 0x42 42
- CLOCK_DIV_CFG Register 0x43 43
- LOGIC_1_CFG Register 0x44 43
- LOGIC_2_CFG Register 0x45 43
- LOGIC_FF_CFG Register 0x46 44
- POLL_TIME_CFG Register 0x48 44
- PIN_CONFIG_A Register 0x49 45
- PIN_CONFIG_B Register 0x4A 45
- PIN_CONFIG_C Register 0x4B 45
- PIN_CONFIG_D Register 0x4C 46
- GENERAL_CFG_B Register 0x4D 46
- INT_EN Register 0x4E 47
- APPLICATION DIAGRAM 48
- OUTLINE DIMENSIONS 49
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