Universal Remote Control R7 - SPECS SHEET Uživatelský manuál Strana 3
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Data Sheet ADP5589
Rev. B | Page 3 of 52
SPECIFICATIONS
VDD = 1.8 V to 3.3 V, T
A
= −40°C to +85⁰C, unless otherwise noted.
1
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
SUPPLY VOLTAGE
VDD Input Voltage Range VDD 1.65 3.6 V
Undervoltage Lockout Threshold UVLO
VDD
UVLO active, VDD falling 1.2 1.3 V
UVLO inactive, VDD rising 1.4 1.6 V
SUPPLY CURRENT
Standby Current I
STNBY
VDD = 1.65 V 1 4 μA
VDD = 3.3 V 1 10 µA
Operating Current (One Key Press) I
SCAN = 10 ms
CORE_FREQ = 50 kHz, scan active,
300 kΩ pull-up, VDD = 1.65 V
30 40 µA
I
SCAN = 10 ms
CORE_FREQ = 50 kHz, scan active,
100 kΩ pull-up, VDD = 1.65 V
35 45 µA
I
SCAN = 10 ms
CORE_FREQ = 50 kHz, scan active,
300 kΩ pull-up, VDD = 3.3 V
75 85 μA
I
SCAN = 10 ms
CORE_FREQ = 50 kHz, scan active,
100 kΩ pull-up, VDD = 3.3 V
80
90
μA
PULL-UP, PULL-DOWN RESISTANCE
Pull-Up Option 1 50 100 150 kΩ
Pull-Up Option 2 150 300 450 kΩ
Pull-Down 150 300 450 kΩ
INPUT LOGIC LEVEL (
RST
, SCL, SDA, R0, R1, R2, R3, R4,
R5, R6, R7, C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10)
Logic Low Input Voltage V
IL
0.3 × VDD V
Logic High Input Voltage V
IH
0.7 × VDD V
Input Leakage Current (Per Pin) V
I-Leak
0.1 1 µA
PUSH-PULL OUTPUT LOGIC LEVEL (R0, R1, R2, R3, R4,
R5, R6, R7, C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10)
Logic Low Output Voltage
2
V
OL
Sink current = 10 mA 0.4 V
Logic Low Output Voltage
3
V
OL
Sink current = 10 mA 0.5 V
Logic High Output Voltage V
OH
Source current = 5 mA 0.7 × VDD V
Logic High Leakage Current (Per Pin) V
OH-Leak
0.1 1 µA
OPEN-DRAIN OUTPUT LOGIC LEVEL (
INT
, SDA)
Logic Low Output Voltage (
INT
)
V
OL
I
SINK
= 10 mA
0.4
V
Logic Low Output Voltage (SDA) V
OL
I
SINK
= 20 mA 0.4 V
Logic High Leakage Current (Per Pin) V
OH-Leak
0.1 1 µA
Logic Propagation Delay 125 300 ns
FF1 Hold Time
4
0 ns
FF1 Setup Time
4
175 ns
FF2 Hold Time
4
0 ns
FF2 Setup Time
4
175 ns
GPIO Debounce
4
70 µs
Internal Oscillator Frequency
5
OSC
FREQ
900 1000 1100 kHz
I
2
C TIMING SPECIFICATIONS
Delay from UVLO/Reset Inactive to I
2
C Access 60 µs
SCL Clock Frequency f
SCL
0 1000 kHz
SCL High Time t
HIGH
0.26 µs
SCL Low Time t
LOW
0.5 µs
Data Setup Time t
SU; DAT
50 ns
Data Hold Time t
HD; DAT
0
µs
Setup Time for Repeated Start t
SU; STA
0.26 µs
- ADP5589 1
- TABLE OF CONTENTS 2
- SPECIFICATIONS 3
- ABSOLUTE MAXIMUM RATINGS 5
- QUICK DEVICE OVERVIEW 7
- 9714-004 7
- DEVICE ENABLE 8
- DEVICE OVERVIEW 8
- EVENT FIFO 9
- KEY SCAN CONTROL 9
- Rev. B 10
- KEY PRESSED 10
- 09714-009 10
- Data Sheet ADP5589 11
- ADP5589 Data Sheet 12
- Key Pad Extension 12
- Ghosting 12
- FIFO Lock/Unlock 12
- GPI Input 15
- REGISTER INTERFACE 19
- REGISTER MAP 21
- ID Register 0x00 23
- INT_STATUS Register 0x01 23
- Status Register 0x02 23
- FIFO_1 Register 0x03 24
- Rev. B 25
- Rev. B 26
- GPI_INT_STAT_A Register 0x13 27
- GPI_INT_STAT_B Register 0x14 27
- GPI_INT_STAT_C Register 0x15 27
- GPI_STATUS_A Register 0x16 28
- GPI_STATUS_B Register 0x17 28
- GPI_STATUS_C Register 0x18 28
- RPULL_CONFIG_A Register 0x19 29
- RPULL_CONFIG_B Register 0x1A 29
- RPULL_CONFIG_C Register 0x1B 30
- RPULL_CONFIG_D Register 0x1C 30
- RPULL_CONFIG_E Register 0x1D 31
- GPI_EVENT_EN_A Register 0x21 32
- GPI_EVENT_EN_B Register 0x22 33
- GPI_EVENT_EN_C Register 0x23 33
- DEBOUNCE_DIS_A Register 0x27 35
- DEBOUNCE_DIS_B Register 0x28 35
- DEBOUNCE_DIS_C Register 0x29 36
- GPO_DATA_OUT_A Register 0x2A 36
- GPO_DATA_OUT_B Register 0x2B 36
- GPO_DATA_OUT_C Register 0x2C 37
- GPO_OUT_MODE_A Register 0x2D 37
- GPO_OUT_MODE_B Register 0x2E 37
- GPO_OUT_MODE_C Register 0x2F 38
- UNLOCK1 Register 0x33 39
- UNLOCK2 Register 0x34 39
- EXT_LOCK_EVENT Register 0x35 39
- UNLOCK_TIMERS Register 0x36 40
- LOCK_CFG Register 0x37 40
- RESET1_EVENT_A Register 0x38 40
- RESET1_EVENT_B Register 0x39 40
- RESET1_EVENT_C Register 0x3A 41
- RESET2_EVENT_A Register 0x3B 41
- RESET2_EVENT_B Register 0x3C 41
- RESET_CFG Register 0x3D 41
- PWM_OFFT_LOW Register 0x3E 42
- PWM_OFFT_HIGH Register 0x3F 42
- PWM_ONT_LOW Register 0x40 42
- PWM_ONT_HIGH Register 0x41 42
- PWM_CFG Register 0x42 42
- CLOCK_DIV_CFG Register 0x43 43
- LOGIC_1_CFG Register 0x44 43
- LOGIC_2_CFG Register 0x45 43
- LOGIC_FF_CFG Register 0x46 44
- POLL_TIME_CFG Register 0x48 44
- PIN_CONFIG_A Register 0x49 45
- PIN_CONFIG_B Register 0x4A 45
- PIN_CONFIG_C Register 0x4B 45
- PIN_CONFIG_D Register 0x4C 46
- GENERAL_CFG_B Register 0x4D 46
- INT_EN Register 0x4E 47
- APPLICATION DIAGRAM 48
- OUTLINE DIMENSIONS 49
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